Cadence Webinars - Entuple Technologies Pvt Ltd

Past Webinars

VLSI (ASIC - Concept to Chip Tapeout)

Agenda	Price
ASIC Design - Evolution, Current Trends, Career Opportunites & Research Avenues for Engineers	FREE
ASIC Front End Design and Verification
Advanced Verification - SystemVerilog and UVM - Need and How to get started ?
ASIC Logic Synthesis and Pre-Layout Timing Analysis
Role of Formal verification and Linting in ASIC Design flow
Physical Implementation flow in ASIC : Guidelines for SoC Designs
Physical Design flow - Floor Plan, Power Plan - Industry perspective
Design for Testability ( DFT) - Evolution and DFT Strategiy for designs
Physical Design flow - Clock Tree Synthesis, P & R
Timing & Power Signoffs in PD flow
Physical Verification flow for SoC Designs
Custom IC Design - Approach and flow
Custom IC Design - Schematic and Layout Design and Analysis
Building Fundamental Analog Blocks - Characterization, Schematic Design & Analysis
Analog & Mixed Signal Design & Simuluation
Concept to Silicon - How you can take your designs into fabrication?

Electronic System Design Series

Agenda	Price
Electronic System Design for Emerging Technologies - IoT, 5G and more	FREE
Electronic Circuit Design and Analysis - Challenges and Solutions
Advanced Electronic System Design & Analysis
Electronic System Design and Product Focus - How to give shape to your design ideas

NOTE: Participants should attend all quiz polling & should maintain minimum 80% attendance for entire event. Only those participants will receive e-certificate.

Coming soon

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