VLSI Design Flow using Cadence EDA Tool – Workshop

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June 13-19, 2016 | VLSI Design Flow using Cadence EDA Tool | PVPIT, Ramnagaria, Bavdhan, Pune| Workshop

VLSI Design Flow using Cadence EDA Tool – Workshop

The aim of this workshop is to provide hands-on Analog & Digitial (ASIC) VLSI Design Flow using the state-of-the-art Cadence EDA tools. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and RC Extraction of Layouts. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).

About Cadence

Cadence is a leading provider of Electronic Design Automation (EDA) and semiconductor IP. Their custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Their digital tools automate the design and verification of Giga-scale, Giga-hertz SoCs at the latest semiconductor processing nodes. Their IC packaging and PCB tools permit the design of complete boards and subsystems.

Cadence also offers a growing portfolio of design IP and verification IP for memories, interface protocols, analog/mixed-signal components, and specialized processors. And reaching up to the systems level, Cadence offers an integrated suite of hardware/software co-development platforms. In short, Cadence® technology helps customers build great products that connect the world.

Cadence India is present in Noida, Bangalore, Pune and Hyderabad. Established in 1987, the Noida site is the largest Cadence R&D site outside the U.S. R&D work done in India focuses on developing design automation solutions to address the needs of advanced technology nodes by leveraging Cadence leadership in EDA technology.

About FDP

One of the major challenges faced by the teachers ,teaching CMOS /ASIC Design at ME Level in VLSI &Embedded System is perhaps how to bridge the concepts to the application and the practice to bring out the practical perspective for an effective teaching – learning interaction.
In addition, the lack of hands–on practices on part of the teachers makes it much more difficult to excite the students’ learning inquisitiveness.
The primary objective of the proposed FDP is to enable the teachers to bridge this gap in between concepts and practical implementation and enhance the effectiveness of teaching the subject through a series of hands–on .and illustrative examples.
The program focuses on CMOS /ASIC Circuits designed with a synthesis approach.. The program also caters to the needs of teachers pursuing their higher studies/ research in custom analog and mixed signal domain.

Who can attend

The workshop is open to Faculty of Engineering colleges, Research Scholars and PG Students. Participants will be expected to have knowledge about VLSI Design.

Detailed Agenda

  • Introduction on CIC Design Flow and ASIC Design flow.
  • CIC Front End Lab Session
  • Schematic capture And Simulation On
    : PDK Device Characterization –
    :NMOS- RCH, Cgs, Cdb
    : PMOS- RCH, Cgs, Cdb
  • CMOS Inverter Schematic Capture and Simulation On
    : Characterization of – VOH, VIL, VOL, VIL, VSP, tpd
    : Parametric Analysis.
    : Basic Amplifier Design concept.
    : Implementation of inverter as an amplifier.
  • Common source Amplifier Design.
    : Simulation and analysis of Amplifiers.
    : Differential Amplifier Design.
  • Basic Layout Concepts – CS Amplifier includes.
  • Layout, DRC, LVS, XRC and Back Annotation. (Back End Design up to GDSII)
    : Basic Layout Concepts – CS Amplifier includes.
  • Layout, DRC, LVS, XRC and Back Annotation. (Back End Design up to GDSII)
  • Discussion on ASIC Design Flow.
    Lab 1: Front Simulation with HDL codes.
    Lab 2: Synthesis using Encounter RTL Compiler.
    Lab 3: Back End Design Using SoC Encounter.
  • Hands on Any two practical of Analog CMOS design of ME.

Duration: 7 Days
Course Fee:
Teaching faculty: INR 10,000
M. Tech. Students: INR 7,000
Download Brochure


To know more:
Mr. Umesh Paladhikar
Email: umesh.paladhikar@entuple.com
Mobile: +91 9687654112
Land Line : 080-42028111

Registration Form

Registration is closed for this seminar.