VLSI Design Flow using Cadence EDA Tool – Workshop

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May 25-26, 2016 | VLSI Design Flow using Cadence EDA Tool | SKIT, Ramnagaria, Jagatpura, Jaipur | Workshop

VLSI Design Flow using Cadence EDA Tool – Workshop

The aim of this workshop is to provide hands-on Analog & Digitial (ASIC) VLSI Design Flow using the state-of-the-art Cadence EDA tools. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and RC Extraction of Layouts. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).

About Cadence

Cadence is a leading provider of Electronic Design Automation (EDA) and semiconductor IP. Their custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Their digital tools automate the design and verification of Giga-scale, Giga-hertz SoCs at the latest semiconductor processing nodes. Their IC packaging and PCB tools permit the design of complete boards and subsystems.

Cadence also offers a growing portfolio of design IP and verification IP for memories, interface protocols, analog/mixed-signal components, and specialized processors. And reaching up to the systems level, Cadence offers an integrated suite of hardware/software co-development platforms. In short, CadenceĀ® technology helps customers build great products that connect the world.

Cadence India is present in Noida, Bangalore, Pune and Hyderabad. Established in 1987, the Noida site is the largest Cadence R&D site outside the U.S. R&D work done in India focuses on developing design automation solutions to address the needs of advanced technology nodes by leveraging Cadence leadership in EDA technology.

Who can attend

The workshop is open to Faculty of Engineering colleges, Research Scholars and PG Students. Participants will be expected to have knowledge about VLSI Design.

Detailed Agenda

  • First day will be the full Analog flow using Virtuoso tool.
  • Second day will be the Digital Design Flow using Encounter and RTL Compiler.

Duration: 2 Days

Download Brochure


To know more:
Mr. Vinay Goel
Email: vinay@entuple.com
Mobile: +91 9810233256
Mr. Raghav Pachaury
Email: easi@entuple.com
Mobile: +91 9599039673
Land Line : 080-42028111

Registration Form

Registration is closed for this seminar.