Analog Integrated Circuit Design using Cadence Analog Design Flow

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June 1-5, 2015 | Entuple Technologies, Bangalore| Paid FDP

‘Bridging Concepts to Practice’ Training Series

One of the challenges in teaching Analog Integrated Circuit Design course to engineering graduates is perhaps to bridge the theoretical concepts to its various applications in real-time.

Our training programs are designed to enable the faculty members in driving an effective teaching – learning interaction. This training program will take you through a series of hands–on illustrative teaching–learning activities/ experiments bridging the theoretical concepts to the industry relevant application perspective as well as practices.

About this FDP
The program focuses on CMOS Analog Integrated Circuits and is designed with a synthesis approach and progressively builds up the background and walks you through an illustrative design and characterization set of learning activities of some of the basic analog functional blocks such as current mirrors, repeaters, and finally, a seven-pack CMOS operational amplifier.
Who can attend

  • Teachers with little or no prior experience of teaching Analog Integrated Circuits
  • Teachers seeking design hands-on insight on Analog Integrated Circuits and pursuing research
  • Tech. (VLSI/ Embedded Systems) and Research Scholars
  • Teachers pursuing their higher studies/research in custom analog and mixed signal domain.

Key learning outcomes

At the end of the program you will be able to

  • Characterize the PDK for device analog model parameters
  • Synthesize basic and OP-AMP amplifier circuit topologies
  • Analyze the Performance Specification Requirements and Identify the suitable circuit topologies
  • Carry out the Design for DC and AC Performance for the various basic CMOS Amplifier circuits
  • Develop programmed spread sheets for amplifier design automation
  • Design and characterize a seven – pack CMOS Compensated OP-AMP at the schematic design entry level
  • Derive Layout Constraints for the Physical Design of the OP-AMP and carry out DRC and LVS clean Physical Design
  • Carry out the Physical verification and Parasitic Extraction
  • Back Annotate and carry out Post Layout Simulation/ Characterization

Detailed Agenda

Day 1: Fundamentals of Analog Signal Processing – CMOS Amplifier Topologies & Performance

  • Review of the generic amplifier performance parameters – Gain, Power Dissipation, Frequency Response, (Noise – optional, time permitting)
  • Synthesis of Basic Amplifier Circuit Topologies
    • Basic Amplifier Circuit Topologies: CS, CD and CG
  • Large and Small Signal DC Performance Analysis and Design of Basic Amplifiers
  • Single and Differential Ended Signaling – Concept Illustration – What really is a common mode signal?
  • The Basic Ideal OP-AMP and its properties
    • What really is virtual short and virtual ground?
  • Lab1: PDK Device Characterization for Analog Model Parameters
  • Lab 2: Hands – on Tutorial on Design and Simulation of a CS Amplifier for Large and Small Signal DC performance
  • Lab 3: Design and Simulation of the Bias Circuit for the CS amplifier: Hands – on Tutorial

Day 2:  Small Signal DC Design and Simulation of the Basic Differential Pair/ Analog Layout Design Concepts

  • Interpreting the Design Specifications
  • Design Methodology and Flow – Large Signal and Small Signal DC Design
  • Analog Layout Design Concepts – Importance of Device Matching in Layouts; LDEs
  • Lab 4: Design and Performance Characterization of CMOS Current Mirror (Schematic Design and Simulation)
  • Lab 5: Layout Design of a CMOS Current Mirror
  • Lab 6: DC Performance Characterization of the Basic CMOS Differential Amplifier (5 – Pack OP-AMP)

Day 3 – 4:  Frequency Response and Compensation of Amplifiers – Performance Analysis

  • Effect of the Amplifier BW limitations on Analog Signal Processing – Illustration
  • Review of Transfer Functions and Frequency Response Plots; FB concepts and Effect of FB on Frequency Response, Stability and Compensation
  • Gain – BW Enhancement Techniques – The CASCODE Stage
  • Small Signal AC Performance of CS and Differential Pair
  • Lab 7: Design and Characterization of the CS amplifier for Small Signal DC and AC Performance
  • Lab 8: Design and Characterization of Differential Pair for Small Signal DC and AC Performance

Day 5:  Design and Performance Characterization of a 7 – Pack OPAMP

  • A Hands-on Tutorial for Schematic and Layout Design of a CMOS OP-AMP for the given Specifications and   Characterization

Duration: 5 Days
No. of participants: 15
Tool used: Cadence Analog Design Flow
Course Fee:

  • Teaching faculty: INR 33,700 (without accommodation)
  • Teaching faculty: INR 45,000 (with accommodation)
  • M. Tech. Students: INR 20,000
  • M. Tech. Student participants will have to make their own accommodation arrangements.
  • Tea and working lunch will be provided at the venue during the program.

Prices are inclusive of all taxes.

Note: Accommodation facility provided only to the participants who have requested for it at the time of registration and against the due advance payment of registration fees as indicated. Accommodation Charges are extra at INR 10,000.00 + 12.36% [ Tax]

 

To know more:
Mr. Jathin K P
Email: cadence_training@entuple.com
Mobile: +91 8951529637
Land Line : 080-42028111

Registration Form

Registration is closed for this seminar.