Analog Integrated Circuit Design using Cadence Analog Design Flow

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Dec 7-11, 2015 |Analog Integrated Circuit Design |Entuple Technologies, Bangalore | Paid FDP

Analog Integrated Circuit Design using Cadence Analog Design Flow

One of the major challenges faced by the teachers   teaching Analog Integrated Circuit Design course at the graduate (1st/ 2nd Semester) levels in Electrical Communications Engineering is perhaps how to bridge the concepts to the application and the practice to bring out the practical perspective for an effective teaching – learning interaction.

In addition, the lack of hands–on practices on part of the teachers makes it much more difficult to excite the students’ learning inquisitiveness.

The primary objective of the proposed FDP is to enable the teachers to bridge this gap and enhance the effectiveness of teaching the subject through a series of hands–on illustrative teaching – learning activities/ experiments bridging the theoretical concepts to the industry relevant application perspective as well as practices.

The program focuses on CMOS Analog Integrated Circuits, is designed with a synthesis approach and progressively builds up the background and walks you through an illustrative design and characterization set of learning activities of some of the basic analog functional blocks such as current mirrors, repeaters, and finally, a seven-pack CMOS operational amplifier. The program also caters to the needs of teachers pursuing their higher studies/ research in custom analog and mixed signal domain.

Key Learning Outcomes

At the end of the program you will be able to

  • Characterize the PDK for device analog model parameters
  • Synthesize basic and OP-AMP amplifier circuit topologies
  • Analyze the Performance Specification Requirements and Identify the suitable circuit topologies
  • Carry out the Design for DC and AC Performance for the various basic CMOS Amplifier circuits
  • Develop programmed spread sheets for amplifier design automation
  • Design and characterize a seven – pack CMOS Compensated OP-AMP at the schematic design entry level
  • Derive Layout Constraints for the Physical Design of the OP-AMP and carry out DRC and LVS clean Physical Design
  • Carry out the Physical verification and Parasitic Extraction
  • Back Annotate and carry out Post Layout Simulation/ Characterization

Course Outline and Structure

Day 1: Fundamentals of Analog Signal Processing – CMOS Amplifier Topologies and Performance

  • Review of the generic amplifier performance parameters – Gain, Power Dissipation, Frequency Response, (Noise – optional, time permitting)
  • Synthesis of Basic Amplifier Circuit Topologies
    • Basic Amplifier Circuit Topologies: CS, CD and CG
  • Large and Small Signal DC Performance Analysis and Design of Basic Amplifiers
  • Single and Differential Ended Signaling – Concept Illustration – What really is a common mode signal?
  • The Basic Ideal OP-AMP and its properties
    • What really is virtual short and virtual ground?
  • Lab1: PDK Device Characterization for Analog Model Parameters
  • Lab 2: Hands – on Tutorial on Design and Simulation of a CS Amplifier for Large and Small Signal DC performance
  • Lab 3: Design and Simulation of the Bias Circuit for the CS amplifier: Hands – on Tutorial

Day 2: Small Signal DC Design and Simulation of the Basic Differential Pair/ Analog Layout Design Concepts

  • Interpreting the Design Specifications
  • Design Methodology and Flow – Large Signal and Small Signal DC Design
  • Analog Layout Design Concepts – Importance of Device Matching in Layouts; LDEs
  • Lab 4: Design and Performance Characterization of CMOS Current Mirror (Schematic Design and Simulation)
  • Lab 5: Layout Design of a CMOS Current Mirror
  • Lab 6: DC Performance Characterization of the Basic CMOS Differential Amplifier (5 – Pack OP-AMP)

Day 3 – 4: Frequency Response and Compensation of Amplifiers – Performance Analysis

  • Effect of the Amplifier BW limitations on Analog Signal Processing – Illustration
  • Review of Transfer Functions and Frequency Response Plots; FB concepts and Effect of FB on Frequency Response, Stability and Compensation
  • Gain – BW Enhancement Techniques – The CASCODE Stage
  • Small Signal AC Performance of CS and Differential Pair
  • Lab 7: Design and Characterization of the CS amplifier for Small Signal DC and AC Performance
  • Lab 8: Design and Characterization of Differential Pair for Small Signal DC and AC Performance

Day 5: Design and Performance Characterization of a 7 – Pack OPAMP

A Hands-on Tutorial for Schematic and Layout Design of a CMOS OP-AMP for the given Specifications and   Characterization

Duration: 5 Days
Place: Entuple Technologies, Bangalore.
Course Fee:

  • Teaching faculty: INR 22,000.00
  • Tech. Students: INR 17,000.00
To know more:
Mr. Jathin K P,
Mobile: +91 8951529637
Email: cadence_training@entuple.com
Land Line : 080-42028111

Registration Form

Registration is closed for this seminar.