VLSI – Custom Digital Design

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Indian Semiconductor Industry and the EDA community has been contributing to the evolution of the necessary competence through several support programs and workshops joining the Indian Government’s initiative, the reach however, has been very limited given the vast number of universities jump starting into offering these courses with little or zero competence on the campuses due to a lack of hands – on silicon expertise available.

In addition, the limited reach available to the numerous campuses to the design resources such as digital standard cell libraries, IO libraries, Memory and Memory and Memory Compilers, Analog and Mixed Signal IPs/ Macros, IO PHY layers, Synthesize Special Function Digital IPs, Verification IPs followed by fabrication and testing facilities, barring the premier campuses and a few NITs, has further compounded the issue of developing the requisite competence on the campuses so much so that majority of the VLSI and Embedded System graduates end up seeking and pursuing career/ job opportunities in the IT sector!

We at Entuple firmly believe in enabling the competence development amongst the academia toward building the necessary ecosystem for the ESDM domain. In line with our vision, Entuple has embarked on a pioneering initiative to provide a comprehensive solution portfolio in terms of an easy and affordable access to the necessary design library resources for pursuing their R & D and Student Project Activities in the VLSI Digital ASIC, Soc and Mixed Signal Domains.


Our design and verification offerings under the custom digital design portfolio include

  • Generic Standard Cell Library Development for both SCMOS and specific technologies all the way down to 90 nm
  • LP, LV and High Speed Standard Cell Libraries
  • Standard Cell Characterization
  • Memory Designs and Memory Compilers
  • General Purpose IO Libraries
  • An assortment of IO protocol PHY layers

Some of our offerings:

  • Cadence VLSI Bundle: Cadence Electronic Design Automation (EDA) tools are extensively used in academic campuses across the world to for teaching and learning purposes in technologies related to VLSI, Logic Design, Logic Synthesis, ASIC/FPGA design courses as well as in various research projects.
  • Training - Analog Integrated Circuit Design using Cadence Analog Design Flow: This 5 day hands-on training is focuses on CMOS Analog Integrated Circuits and is designed with a synthesis approach and progressively builds up the background and walks you through an illustrative design and characterization set of learning activities of some of the basic analog functional blocks such as current mirrors, repeaters, and finally, a seven-pack CMOS operational amplifier. (know more)

Please write to us for a detailed list of products & value added services related to VLSI Custom Digital Design.