Entuple Technologies is committed to provide a complete bundle of learning-enabler solutions to our academic customers related to VLSI ASIC/SoC design.
Our design and verification offerings under the digital ASIC/ Soc Design and verification portfolio encompasses
- Synthesizable IPs (RTL) for an digital functional blocks including high speed DSP functional block sets
- Synthesizable IO protocols
- Memory and Microcontroller Interface Protocols
- High Speed Arithmetic Functions
- Verification IPs for an assortment of functional blocks and IPs
- Design support for Physical Design and Verification
- Complete Chip Integration
Some of our products:
- Cadence VLSI Bundle: Cadence Electronic Design Automation (EDA) tools are extensively used in academic campuses across the world to for teaching and learning purposes in technologies related to VLSI, Logic Design, Logic Synthesis, ASIC/FPGA design courses as well as in various research projects.
- OrCAD PSpice Simulation Bundle: OrCAD® PSpice® and Advanced Analysis technology combine industry-leading, native analog, mixed-signal, and analysis engines to deliver a complete circuit simulation and verification solution. Some of the key features include
- Training - Analog Integrated Circuit Design using Cadence Analog Design Flow: This 5 day hands-on training is focuses on CMOS Analog Integrated Circuits and is designed with a synthesis approach and progressively builds up the background and walks you through an illustrative design and characterization set of learning activities of some of the basic analog functional blocks such as current mirrors, repeaters, and finally, a seven-pack CMOS operational amplifier. (know more)
Please write to us for a detailed list of products & value added services related to VLSI ASIC/SoC Design.