Cadence VLSI Bundle

Home / Academic / Products / Cadence VLSI Bundle

We believe in enabling competence development amongst the academia to help evolve India as the world’s leading force to reckon with in ESDM domain. In line with our vision, we are committed to provide a comprehensive solution portfolio in terms of an easy and affordable access to the necessary design library resources for pursuing their R & D and Student Project Activities in the VLSI Digital ASIC, Soc and Mixed Signal Domains.

Our portfolio offers resources over the entire spectrum of VLSI Chip Design Life Cycle to the academia, covering the following

  • Custom Digital IC Design and Verification
  • Custom Analog/ Mixed Signal Design and Verification
  • Digital ASIC Design and Verification
  • Fabrication and Post Silicon Testing

Cadence VLSI tools are available in three bundles.

University UG Bundle

University Bundle Analog & Digital FE & BE for UG courses

Virtuoso Multi‐mode Simulation with AP Simulator 90003
Virtuoso(R) Schematic Editor XL 95115
Virtuoso(R) Analog Design Environment XL 95210
Virtuoso(R) Layout Suite XL 95310
AMS Designer with Flexible Analog Simulation 70020
Incisive Enterprise Simulator ‐ XL 29651
Virtuoso Digital Implementation 3003
Cadence® Physical Verification System Design Rule Checker XL 96210
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220
Encounter RTL Compiler Low Power Option RC200
Virtuoso QRC Extraction ‐ XL QRCX300
University PG Bundle

University Bundle Analog & Digital FE & BE for PG courses

Virtuoso Multi‐mode Simulation with AP Simulator 90003
Virtuoso(R) Schematic Editor XL 95115
Virtuoso(R) Analog Design Environment XL 95210
Virtuoso(R) Layout Suite XL 95310
AMS Designer with Flexible Analog Simulation 70020
Virtuoso AMS Designer Verification Option 70030
Incisive Enterprise Simulator ‐ XL 29651
Encounter RTL compiler RC200
Encounter RTL Compiler Low Power Option RC300
Encounter Conformal Low Power ‐ XL CFM500
Encounter (TM) Conformal ‐ XL (a.k.a Conformal Ultra) CFM200
Encounter Low Power GXL Option EDS10
Encounter Mixed Signal GXL Option EDS20
Voltus IC Power Integrity Solution – XL (VTS‐XL) VTS200
Encounter Digital Implementation System XL EDS200
Tempus Timing Signoff Solution XL TPS200
Cadence® Physical Verification System Design Rule Checker XL 96210
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220
Virtuoso QRC Extraction ‐X L QRCX300
Virtuoso Liberate Server ALT110
Virtuoso Liberate Client ALT111
Virtuoso Variety Server ALT210
Virtuoso Variety Client ALT211
Virtuoso Liberate MX Server ALT410
Virtuoso Liberate MX Client ALT411
Virtuoso Variety MX Server ALT510
Virtuoso Variety MX Client ALT511
Virtuoso Liberate LV Server ALT610
Virtuoso Liberate LV Client ALT611

 

University Research Bundle

 

Virtuoso Multi‐mode Simulation with AP Simulator 90003
Virtuoso(R) Schematic Editor XL 95115
Virtuoso(R) Analog Design Environment XL 95210
Virtuoso(R) Layout Suite XL 95310
AMS Designer with Flexible Analog Simulation 70020
Virtuoso AMS Designer Verification Option 70030
Incisive Enterprise Simulator ‐ XL 29651
Encounter RTL compiler RC200
Encounter Timing System‐XL FE725
Encounter Conformal Low Power ‐ XL CFM500
Encounter RTL Compiler Low Power Option RC300
Encounter Digital Implementation System XL EDS200
Cadence® Physical Verification System Design Rule Checker XL 96210
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220
Virtuoso QRC Extraction ‐ L QRCX300
Virtuoso® Analog Oasis Run‐Time Option 32100
Cadence(R) Design Framework Integrator's Toolkit 12141
Spectre Extensive Partitioned Simulator 91600
Spectre Characterization Simulator Option 3500
Layout
Virtuoso® Layout Suite ‐ GXL1 95321
Cadence® Chip Assembly Router2 3300
Physical Verification
Assura™ Design Rule Checker 72110
Assura™ Layout vs. Schematic Verifier 72120
Virtuoso® QRC Extraction ‐ XL QRCX300
Virtuoso® Advanced Analysis GXL option QRCX310
Assura™ Graphical User Interface Option 72140
Assura™ Multiprocessor Option 72150
Pcell Generator PASPCG
Graphical Technology Editor PASGTE
Cadence® Physical Verification System Design Rule Checker XL 96210
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220
Cadence(R) Design Framework II 111
Cadence QRCX Display Technology Option QRCX330
Cadence QRC Advanced Modeling20 GXL Option QRCX520
Circuit Simulation
Virtuoso® Analog Design Environment ‐ GXL 95220
Virtuoso® RelXpert 33580
AMS Designer with Flexible Analog Simulation 70020
Virtuoso AMS Designer Verification Option 70030
Virtuoso® Multi‐mode Simulation with AP Simulator 90003
Virtuoso Accelerated Parallel Simulator 91050
Virtuoso Multi‐mode Simulation Power option 91400
Virtuoso Multi‐mode Simulation CPU Accelerator option 91500
Virtuoso(R) Power System XL VPS200
Device modelling
Virtuoso Advanced Device Modeling HVMOS (For Eldo) P6191
Virtuoso Advanced Device Modeling HVMOS (For HSPICE) P6192
Digital Integrated Circuits
First Encounter ‐ XL (aka Cadence (R) First Encounter ‐ GPS) FE100GPS
ETS Advanced Analysis GXL Option FE830
Formal Verification
Encounter™ Conformal ‐ CONFRML91GXL CFM300
Encounter Conformal Low Power ‐ GXL CFM550
Encounter Conformal Low Power ‐ XL CFM500
Synthesis
Encounter™ RTL Compiler ‐ XL RC 101 RC200
Encounter RTL Compiler CPU Accelerator Option RC302
Encounter RTL Compiler Low Power Option RC310
Encounter RTL Compiler Advanced Physical Option RC340
C‐to‐Silicon Compiler ‐ L CTS102
Test
Encounter™ True Time Test Advanced ET91 ET023
Encounter Diagnostics Basic ET010
Option to RC ‐ DFT Architect Basic ET020
Option to RC ‐ DFT Architect Advanced ET021
Encounter True Time ATPG Basic ET022
Chip Planning
Cadence® InCyte Chip Estimator XL CICE40 CPS200
Functional Verification
Cadence® Simulation Analysis Environment (SimVision) IUS82 25010
Incisive™ Enterprise Simulator 29651 IES82 29651
Enterprise Simulator ‐ XL Interface for MTI IES82 29661
Enterprise Simulator ‐ XL Interface for VCS IES82 29671
Incisive™ Formal Verifier IFV82 23560
Incisive™ Enterprise Verifier ‐ XL IFV82 IEV101
Incisive™ Software Extensions INCISV102 ISX100
Virtuoso® AMS Designer Verification Option INCISV102 70030
Digital Mixed Signal Option to IES 29710
Verification Process Automation
Incisive™ Enterprise Manager EMGR82 EMG100
Litho Physical Analyzer LPA108
Litho Electrical Analyzer LEA108
Signoff Power Analysis
Virtuoso(R) Power System XL VPS200
Voltus IC Power Integrity Solution – XL (VTS‐XL) VTS200
Voltus IC Power Integrity Solution Advanced Analysis GXL (VTS‐AA) VTS201
Signoff Timing Analysis
Tempus Timing Signoff Solution L TPS100
Tempus Timing Signoff Solution XL TPS200
Tempus Timing Signoff Solution TSO TPS300
Tempus Timing Signoff Solution MP TPS400
Signal Integrity
PacifIC Static Noise Analyzer for Custom Digital ICs PACIFIC61 CM00100
Characterization
Virtuoso Liberate Server ALT110
Virtuoso Liberate Client ALT111
Virtuoso Variety Server ALT210
Virtuoso Variety Client ALT211
Virtuoso Liberate MX Server ALT410
Virtuoso Liberate MX Client ALT411
Virtuoso Variety MX Server ALT510
Virtuoso Variety MX Client ALT511
Virtuoso Liberate LV Server ALT610
Virtuoso Liberate LV Client ALT611
Silicon Virtual Prototyping
Encounter™ Digital Implementation System ‐ XL EDI91 EDS200
Encounter™ Low Power GXL Option EDI91 EDS10
Encounter™ Advanced Node GXL option EDI91 EDS30
Encounter Mixed Signal GXL Option EDS20
Encounter Giga Scale GXL Option EDS70
Encounter DFM GXL Option EDS50
Digital System‐In‐Product (SIP)1
Cadence® SiP Digital SI ‐ XL SIP215 SPB163 SIP215
Cadence SiP Digital Architect ‐ XL SIP110
Silicon‐Package‐Board
PCB Design and Layout
Allegro® PCB Librarian ‐ XL PX3500 SPB163 PX3500
Allegro(R) Physical Viewer PX3600
Allegro PCB Designer PA3100
Allegro PCB High‐Speed Option PA3110
Allegro PCB Miniaturization Option PA3120
Allegro PCB Analog/RF option PA3420
Allegro PCB Routing Option PS3500
Allegro Design Authoring High‐Speed Option PA1410
Allegro FPGA system Planner option PA8610
PCB Circuit Design
Allegro AMS Simulator PS2200
Allegro AMS Simulator SLPS interface PA2212
PCB High‐Speed Analysis
Allegro® Sigrity SI base PA5700
Allegro Sigrity Power Aware SI option SIGR915
Allegro Sigrity system Serial Link Option SIGR935
Allegro Sigrity Package Assessment and Extraction Option SIGR945
Power Intigrity
Allegro Sigrity PI base PA5800
Power Integrity Signofff and optimization Option SIGR925
IC Packaging
Cadence® SiP Layout ‐ XL SIP225 SPB163 SIP225
Cadence 3D Design Viewer PA6605

 

 

Entuple Technologies is the Cadence® Channel Partner in India for the university segment. (know more)

Explore our 5-day Faculty Development Program (FDP) on Analog Integrated Circuit Design with Cadence Analog Design Flow

Write to us to know more about our offerings - Training, product bundles, pricing models and licensing options.